On Tue, 17 Jun 2008 05:07:01 +0300
Aapo Tahkola <[EMAIL PROTECTED]> wrote:
> 
> I once wrote an algo that had the ability to remove all write masks and
> swizzles of all instructions that do not contribute to the results.
> Simply dropping instructions with no write mask implements dead code
> elimination.
> Following that, instructions can be divided into two groups:
> -instructions that have fixed output and thus determine which
> components of temporary registers must be fixed
> -instructions where all result components correspond to same
> calculation(mad, xpd, ...)
> 
> By properly combining these two you'd get optimal temporary register
> usage. IIRC, the problem I did not solve was how to rearrange
> instructions of two or more distinct calculations that join up later in
> the program so that you'd use minimal amount of temporary
> registers.
> 

Hi Aapo,

For reordering instruction we need somethings like SSA to first
have a dependency graph btw instruction temporary so we know which
order you need to respect. LLVM use SSA to do some of its optimization.
But my concern with LLVM is that their IL doesn't have any information
on GPU specificity (write mask, swizzling, pre/post op, ...) and i
think it's harder to had such things to LLVM than to do SSA algorithm
or other optimization directly on TGSI (accessed through an array for
ease of use).

I still think LLVM is the way to go when generating code for CPU :)
And i also think that any optimization architecture should be in
mesa so other driver can take advantage of it and add their own
pass.

Cheers,
Jerome Glisse <[EMAIL PROTECTED]>

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