On Fri, 2009-01-30 at 00:03 +0000, Peter Clifton wrote: > On Thu, 2009-01-29 at 15:08 -0800, Eric Anholt wrote: > > We can support any combination of (a8r8g8b8, x8r8g8b8, r5g6b5) x > > (z0,z24,z24s8) > > on either class of chipsets. The only restriction is no mixing bpp when > > also > > mixing tiling. This shouldn't be occurring currently. > > Slightly hijacking, since this isn't a direct comment on the above > patch.. > > I think it might be useful to expose some combinations with 0 alpha > bits. If we don't, there is no obvious way of flagging when you're > mapping a 24bit depth X Pixmap onto a texture. > > The setTexBuffer hook can look at the fbconfig of the GLXPixmap the > texture is targeting, but can't (as far as I could figure out) inspect > what format the X server knows the data is in (we have "cpp" from DRI2, > but that doesn't tell us if the alpha channel is used or not).
That's what this patch was about -- exposing FBconfigs with 0 alpha bits, so that your compositor had some hope of doing the right thing. The other combinations were "well, why not". Though the server is somehow killing the reporting of r5g6b5 on my a8r8g8b8 system. You also may want to look at what clutter is doing for an alternative method of expressing the information for TFP in case of emergency, using TexImage to create storage and then letting it get thrown away. -- Eric Anholt [email protected] [email protected]
signature.asc
Description: This is a digitally signed message part
------------------------------------------------------------------------------ This SF.net email is sponsored by: SourcForge Community SourceForge wants to tell your story. http://p.sf.net/sfu/sf-spreadtheword
_______________________________________________ Mesa3d-dev mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/mesa3d-dev
