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Peter Clifton wrote:
> On Thu, 2009-01-29 at 15:08 -0800, Eric Anholt wrote:
>> We can support any combination of (a8r8g8b8, x8r8g8b8, r5g6b5) x 
>> (z0,z24,z24s8)
>> on either class of chipsets.  The only restriction is no mixing bpp when also
>> mixing tiling.  This shouldn't be occurring currently.
> 
> Is it worth adding these in the intelInitScreen() path as well as the
> intelInitScreen2() path?

In the non-DRI2 case, we can't create these various mismatched visuals.
 We can only create visuals where the buffers match the statically
allocated front, back, depth, and stencil buffers.  In these cases, all
of the buffers are always present (because they're statically
allocated), so there is no point in, for example, exposing a visual that
doesn't have a depth buffer.

In DRI2, we actually allocate the buffers in the visual.  In that case,
there is a difference in the memory used by visuals with and without a
depth buffer.

> I guess the zero-copy TFP problem they were added to help fix is only
> present in the DRI2 enabled case, but should similar FBConfig be added
> to both for consistency?

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