On Tue, 27 Aug 2002, Patriek Lesparre wrote: > >And also, if the ESE FPGA project belongs to the MSX Association or > >not. Personally, I think that if the MSX Association wants to make money > >with the hardware developed by Tsujikawa, then I also want. For me it's > >not clear what is the goal of ESE. > > ESE FPGA project is NOT part of MSX Association. It is a hobbyist project > to create a MSX system on FPGA. The only connection with MSX Association is > that Tsujikawa has expressed his intention to offer them his work.
In this case, many things become easier. I will talk to him, or with his associates, unless he changed his mind and is working together with MSX Association. > >The fact that the japanese language is too far different from the others > >is not an excuse for learning English, for example. If they were able to > >develop the best electronic products, why can't they develop communication > >skills? > > Their culture is so different from ours it's impossible to communicate at > the same level as you do with most of the rest of the world. Even if a > japanese person speaks perfect english, his usage and interpretation of the > language will still differ from yours. > In other words, a language barrier can be broken, but a culture barrier is > far more difficult to break. Well, when almost the entire world speaks and understands English, I think that they don't have a choice. > >The pin layout (the official name is "Pin Assignment") is easy to change > >and is not informed in the VHDL code. > > Then what is the problem? There are several. Let's try to solve some of them right now: The chip-replacement idea: I like this idea because I can isolate problems, i.e., I don't take the chance of designing a new board and having several problems, I just remove the original chip, connect the FPGA, and start do write the code. With this I can be sure that all the other parts of the MSX is working (since the original MSX used for testing is not defective). I seems to be that Tsujikawa doesn't like to use old parts of any MSX. When we does this, his design doesn't need to be pin-compatible with the original chip. This complicates a lot the testability in my lab. Some intro to VHDL: when I say that pin-assignment is not part of the VHDL code, I mean that the VHDL does not decide that the pin 48 of my FPGA will be used as a clock input. This is one of the users task when he wants the CAD tool to sinthesize the chip. But the VHDL HAS TO SPECIFY which signals the chip will receive and send from the "external world". This means that the pin number is not previously specified, but its function and direction (in, out, inout) has to be. As a consequence, if I have to interface the chip to the original MSX, I have to create signals RST, CLK, BC1, BC2, BDIR, and so on, but if I don't want to test it directly in a MSX, the interface block of the chip becomes unnecessary. When you don't implement the interface block, you can change the architecture of the circuit (usually it becomes simplifiable) in a level that, for another coder to readapt it for running in a original MSX, the coder needs to rewrite almost 50% of the code. In some cases, it becomes easier to start from scratch instead of modifying an original FPGA project. Second and most important point: when you design a digital circuit, in general you need flip-flops and/or latches. In VHDL, you can specify explicitly when and where you want the flip-flops to be connected. But if you have a signal and, for some specified conditions, you assign a value, and for all the other conditions you don't assign anything, the CAD tool automatically infers that a latch has to be used, and adds it to the design, in synthesis-time. All hardware-developers that I know simply HATE this coding-style, because it masks some mistakes that the coder uses to make. The most common mistake is to forget to assign a value to a signal in all the possible conditions, i.e., forget to use the directive ELSE in VHDL. When you use the automatic inference method, you should not use the ELSE, and it becomes more difficult to detect when a missing ELSE is right or wrong. Third and critical point: to ease the synthesizer's work (CAD tool's work), and get better results, the coder should never mix sequential and combinational processes. Mixed processes are easier to write, but more difficult to debug and frequently leads to latch inference. So, many VHDL coders create sequential process, which means processes that only describes flip-flops and latches. These kind of process only assign a fixed value for a flip-flop or latch output when a reset signal is received, or just transfer its inputs to the outputs when a rising (or falling) clock edge is received. The combinational process makes all the remaining parts of the code (arithmetic, logical, etc.) These are the main topics. By following these rules we can share some hardware designs and develop chips in a group. Of course there are other rules, but they can be explained when needed. The above rules are essential, they facilitate the comprehension of the code and leads to better results (designs that run with higher clock speed and demands less FPGA area). Any doubts? Don't hesitate to ask me. ----------------------------------------------------------- Marco Antonio Simon Dal Poz http://www.lsi.usp.br/~mdalpoz [EMAIL PROTECTED] "old Fords never die, just get better" _______________________________________________ MSX mailing list ([EMAIL PROTECTED]) Info page: http://lists.stack.nl/mailman/listinfo/msx
