Le lundi 21 FÃvrier 2005 23:49, Attila Kinali a Ãcrit : > On Mon, 21 Feb 2005 23:31:02 +0100 > > Nicolas Boulay <[EMAIL PROTECTED]> wrote: > > You don't plan to tape out an asic by end of june ?! > > I think Timothy knows what he is doing.
sur. I work for a compagny that produice chips for space program. We need 18 month or more to do it. > > > The fpga board could help debugging, and if you're lucky asic could be > > ready for decembre. > > Does it really take half a year from tape out to series production ? > I thought that was in the 3-4 months range ? An asic, in the "normal" compagny need a year. But a graphical design look really complex. > But anyways, this leads to the next question of a project schedule. > This isn't an OSS but a busines project, thus we should all agree > on a somewhat tight schedule until when we want to have certain > things finished. FPGA could come much earlier than asic. no problem for that. And the risk is much lower. > > But don't forget, the debugging that need to be done. Software model did > > not replace engenering model. > > C is not VHDL/Verilog :) And FPGA are real things. With true stupid analog effect... (A ! the actel fpga...) nicO > > > Attila Kinali _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
