On Monday 21 February 2005 16:20, Timothy Miller wrote:
> I had mentioned earlier that I've been tied up with the business
> aspects of the OGP, and I thought some of you might be interested in
> hearing about what's going on and have some discussion on it.
>
> Our research indicates the best potential for success is with a
> two-pronged approach.  One is to sell an ASIC in bulk for embedded
> systems, and the other is a PCB-based version for retail.  As such,
> we have turned our attention, for the moment, to the embedded market
> where we and others feel that we can sell the highest volumes.  To
> compete in that market, of course, we will have to develop an ASIC.
> As such, that will likely be the new primary direction of the OGP.

Is it really a new direction?  The FPGA would still need to remain the 
primary focus of development, both to evolve quickly and reduce the 
frequency of ASIC bugs.

> The retail graphics board will be affected such that the board will
> now sell with a much lower retail price.  Furthermore, we're looking
> into the idea of selling the retail board through partners who
> specialize in that so as to further reduce the price.  The result
> will be a MUCH less expensive retail product.  There is also a
> likelihood that we'll have greater freedom in terms of power
> consumption versus speed.

Ah, that reminds me, a really big selling point for this card would be 
open power management specs, particularly if embedded is going to be a 
target market.

> At the same time, we don't want to leave behind those who would like
> to tinker.

Good to hear.  Also, don't forget the group that doesn't want to wait 
the extra time for an ASIC.  And the group that wants to support the 
project sooner rather than later by purchasing a card as a 
quasi-donation.

> In any case, we will have to design a prototype board, 
> and so our plan is to sell that as a product in its own right.  Some
> changes to it include possibly separating the host controller out
> into a separate chip so that you can reprogram the main FPGA as you
> like without affecting your ability to reprogram it again.

That would be wonderful.  And can we now have the logic to reset/reload 
the FPGA entirely under software control?

> Putting  it another way, the prototype will be designed with features
> that lend themselves more effectively towards experimentation.  The
> lower sales volumes of this product will increase its cost relative to
> the original plan.  If, however, we get higher volume than expected,
> the price will go down, especially for bulk orders.

The lower cost ASIC should be partly applied to subsidizing the cost of 
the FPGA boards.  This will certainly be a business win, by expanding 
the community of developers, alpha testers and general boosters.  Also, 
please don't forget the possibility of a (community sponsored) donation 
program aimed at purchasing FPGA boards for developers.

> While prototypes and experimenter versions of the board will likely
> be identical, they may or may not have the same sale price.  There
> will be more than one prototype board, because we'll support various
> interfaces including PCI, AGP, PC/104, and some others used in
> embedded systems. (PCI Express will be a follow-on; we expect to use
> an external chip to help with that.)  We need to guage how many
> prototypes to make for the initial build.

Can we go to the XC3S4000 then?  We've already nearly eaten the 2000's 
entire multiplier budget in the rasterizer alone.  Without dedicated 
multiplliers, the fragment processor will bloat up and consume vast 
swaths of gates even with 8 bit arithmetic.  We really need some more 
dedicated multipliers.  I'm not saying it can't be done within the 
current confines but I suspect that with the 2000, the fragment 
processor is going to be a big bottleneck even for simple fixed 
function bilinear + alpha, and will bloat up so much that other 
important features such as RGB-YUV conversion will be pushed aside.

Regards,

Daniel
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