On Mon, 21 Feb 2005 23:49:06 +0100, Attila Kinali <[EMAIL PROTECTED]> wrote:
> On Mon, 21 Feb 2005 23:31:02 +0100
> Nicolas Boulay <[EMAIL PROTECTED]> wrote:
> 
> > You don't plan to tape out an asic by end of june ?!
> 
> I think Timothy knows what he is doing.
> 
> > The fpga board could help debugging, and if you're lucky asic could be ready
> > for decembre.
> 
> Does it really take half a year from tape out to series production ?
> I thought that was in the 3-4 months range ?
> 
> But anyways, this leads to the next question of a project schedule.
> This isn't an OSS but a busines project, thus we should all agree
> on a somewhat tight schedule until when we want to have certain
> things finished.

The complete business plan incorporates a schedule, including the
schedules of the engineers working on the commercial side.  We will
inform everyone of that when it's completed so the community can
coordinate.

I've kinda gotten past the bleary-eyed excitement of "open source
friendly graphics", and now I'm concentrating on making sure that the
business based around it is successful without compromising the
original thrust.  It's not just about being open but also about being
able to stay afloat so that the open products continue to be available
for a long time to come.  The FOSS community really needs this kind of
thing.  Sink or swim, whatever happens here is going to send a REALLY
HUGE message.  I want that to be the RIGHT message.



> 
> > But don't forget, the debugging that need to be done. Software model did not
> > replace engenering model.
> 
> C is not VHDL/Verilog :)
> 
>                         Attila Kinali
> 
> --
> éãåããéãåã
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