On Tuesday 27 December 2005 01:50, Timothy Miller wrote: > Is it still a problem if the reset is held active for a long time? > That's always how I've done it. I've made sure that the reset was > active for at least a few cycles in the slowest clock domain.
Setting the reset is not the problem; resetting it is. When the reset signal is reset asynchronously, some FFs may still be reset on that clock edge, while others are updated in accordance with the code. This can create very interesting behaviour of your design after a reset. > Can you get glitches if you do sync reset on a single reset signal? > Or should we ensure that there's a valid reset for each individual > clock domain? A reset should be valid for each clock domain, though as with most signals you can just transfer it to the proper clock domain using 2 FFs. > tail0 is where you're writing. > tail1 is what you compare against head4 to determine if the fifo is full. > tail2 is what you compare against head4 to determine is you're going > to be full on the next cycle. > tail3 is just a combinatorial 'increment' of tail2. I understand, but are all those comparison signals needed? I still feel it would be enough to use the current pointer for writing, and the next pointer for full-checking (meaning 2 copies i.s.o. 4). Considering that it's late here, I'll probably make mistakes if I do it now, but if you don't mind I'd like to have a look at an alternative implementation, just for comparison, tomorrow, and send it to this thread. It'll also be a good opportunity for me to check how bad my Verilog understanding truly is. :) Regards, Pieter _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
