---------- Forwarded message ---------- From: howard parkin To Arthur,
The intention was to allow the following methods to reprogram the SPI PROM on the big FPGA. 1) Via JTAG from ispLEVER software. 2) Via JTAG controlled from the small FPGA. 3) Via register interface accessible from PCI. We got 1) and 2) above but only 3/4 of 3). The Lattice ECP2 device has two types of configuration pins, 'dedicated' and "dual purpose'. The dual purpose pins are available after configuration providing certain rules are met. It explains this in TN1108 in the section headed "Configuration Pins". The dual purpose pins were to be connected to a soft SPI interface that we would code and this interface would provide register access via PCI. However, the CCLK pin is a dedicated pin used only during configuration, and is not accessible from the core logic of the FPGA. After configuration, it becomes an unused input. To access this clock, it is necessary to tie an additional I/O pin to the CCLK pin. Somewhere along the line, probably the 4th or 5th time I re-did the pin-out for the big device, that connection got lost. I will put it back on the next schematic revision. Howard On 3/5/06, Timothy Miller <[EMAIL PROTECTED]> wrote: > Can you make sense of what he's talking about? He seems to be > suggesting that the ECP will have control of a signal that we need for > reprogramming the SPI. > > > ---------- Forwarded message ---------- > From: Arthur Jones <[EMAIL PROTECTED]> > Date: Mar 5, 2006 8:48 AM > Subject: Re: [Open-graphics] soft reprogramming [was: Off topic sexy > idea for OGP] > To: Timothy Miller <[EMAIL PROTECTED]> > Cc: [email protected] > > > hi tim, ... > > On Wed, Mar 01, 2006 at 07:43:43PM -0500, Timothy Miller wrote: > > [...] > > And of course, the small FPGA can reprogram the SPI prom that the big > > FPGA uses to program itself on startup. > > i guess the implication of this decision is that > we would need to do multi-master spi. this means that > the big fpga would need to release the spi mosi and > ce# lines when it is done reconfiguring. i could not find > anything in the data sheet that implies that it will, > in fact, in the tech note on configuration (TN1108) > they seem to imply that mosi gets driven as an output > when in spi configuration mode (bottom of page 13-5). > the revb schematic also shows both as outputs only. > without cooperation from the big fpga, multi-master > won't work. i have not looked super carefully yet, > though -- maybe there is some way for the config > pins to be released internally. someone who knows > that chip better (i've never used it) might know... > > if the current method doesn't work out, another possibility > would be to have the small fpga keep the big fpga in > reset until it is ready, then it could fake the spi > sequence (look like an spi prom) to the big fpga. this > would have the advantage of needing only one prom and > it should be pretty easy to implement, prob you could > just route the lines through. the main disadvantage > is that you would always need a working small fpga... > > also, i haven't checked all the spi related lines > carefully yet as seaching the schematics without text > is just too time consuming (hopefully this gets fixed > soon with the conversion to geda)... > > arthur > _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
