I'm making this up as I go along, so I'm not sure if I'm skipping over
something or not. Before we go further, I figure we should have a
short quiz.
Explain this code in detail:
module whatsit(a, b, d, c);
input [3:0] a, b;
input d;
output [3:0] c;
wire [3:0] e, f;
assign e = a & b;
assign f = a + b;
assign c = d ? e : f;
endmodule
To shift this into C:
char whatsit( char a, char b, bool d )
{
if( d ) return a & b;
else return (a + b) & 0x0F;
}
The carry bit from the addition is being lost (hence the & 0x0F at the end of the addition). Also char is 4 bits wider than the types of the Verilog, but it's the nearest C equivalent.
Do I win?
Tom
_______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
