James Richard Tyrer wrote:
The logic cost of generating and using the refresh enable appears to
be small. It is turned on when the last pixel of the scan line is
loaded into the FIFO and turned off a fixed number of clocks before
the end of horizontal sync (to allow for the start of fetching the
pixels for the next line).
Based on Timothy's description of the video controller, you will have
about half a scan line during which the refresh enable will be active.
Due to the fact that the video controller loads pixel data one scanline
prior to it's use, a refresh period interrupting the data transfer would
not glitch the screen so long as the cumulative refresh time did not
delay the video controller memory read by more than about half a
scanline. An active memory request from the video controller de-asserts
the "opportunistic" refresh enable. Should a required refresh window
occur during video controller memory access, it will take priority and
interrupt the request.
Patrick M
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