Patrick McNamara wrote:
James Richard Tyrer wrote:
The logic cost of generating and using the refresh enable appears to
be small. It is turned on when the last pixel of the scan line is
loaded into the FIFO and turned off a fixed number of clocks before
the end of horizontal sync (to allow for the start of fetching the
pixels for the next line).
Based on Timothy's description of the video controller, you will have
about half a scan line during which the refresh enable will be active.
Due to the fact that the video controller loads pixel data one scanline
prior to it's use, a refresh period interrupting the data transfer would
not glitch the screen so long as the cumulative refresh time did not
delay the video controller memory read by more than about half a
scanline. An active memory request from the video controller de-asserts
the "opportunistic" refresh enable. Should a required refresh window
occur during video controller memory access, it will take priority and
interrupt the request.
There are trade offs here that will probably require modeling to resolve.
If a refresh interrupts the screen refresh read, it will cause a row
miss in the video memory block. This row miss can be avoided using the
method described above.
If you read the screen refresh as a block there will be no other access
to memory while this is happening. This will probably slow down the
GPU. The screen refresh does need to be able to preempt other bus
masters, but only when the FIFO is running low. Otherwise, it can read
whenever an empty slot in the memory access pipeline is available.
Screen refresh could be interleaved with other memory access to keep the
pipeline full. However, if you do that, there will be some row misses
when reading video memory.
There is no 100% best answer here. That is the way design works. Also,
avoiding a few hundred row misses per second isn't a big deal. But,
designs are improved by small increments.
--
JRT
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