James Richard Tyrer wrote:
Dieter wrote:
So, are we going to use "eight 128 megabit chips" on the OGC to have
a 128 bit buss?
Do we make a place on the board for the extra chip?
8 bits for each 64 bits? IIRC
That is 7 bits for the code and one for parity which triggers the error
correction interrupt.
--
JRT
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