Timothy Normand Miller wrote:
On 2/13/07, James Richard Tyrer <[EMAIL PROTECTED]> wrote:
A real FIFO uses an extra bit which is set when data is written and
cleared when it is read. Perhaps this would work with memory based
FIFO. If you has a "dirty" bit, then you wouldn't need to compare
addresses to determine if the FIFO was empty. If the memory location at
the tail pointer had the dirty bit set, then it would read out that
memory location, clear the dirty bit and increment the counter. The
head pointer would avoid overrun by not writing to a memory location
till the dirty bit was clear.
We thought about that. The writer sets the bit, and the reader clears
it. But that would require a 3-port block RAM, which we don't have.
You can't use the same memory for the dirty bits. They are going to
have to be separate from the data ram. This doesn't need to be actual 3
port ram since you have one port that is read only and two ports that
are write only and the write ports have arbitration depending on whether
the bit is 1 or 0 -- only one write port can be active at a time and
this is automatically arbitrated by the FIFO logic. You could use
synchronous SR flipflops for this if 512 flipflops isn't too much real
estate.
--
JRT
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