On 2/13/07, James Richard Tyrer <[EMAIL PROTECTED]> wrote:
Timothy Normand Miller wrote:
> On 2/13/07, James Richard Tyrer <[EMAIL PROTECTED]> wrote:
You can't use the same memory for the dirty bits. They are going to
have to be separate from the data ram. This doesn't need to be actual 3
port ram since you have one port that is read only and two ports that
are write only and the write ports have arbitration depending on whether
the bit is 1 or 0 -- only one write port can be active at a time and
this is automatically arbitrated by the FIFO logic. You could use
synchronous SR flipflops for this if 512 flipflops isn't too much real
estate.
Understood. We'd just like to avoid wasting a block RAM for a
one-bit-wide fifo.
--
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Favorite book: The Design of Everyday Things, Donald A. Norman, ISBN
0-465-06710-7
_______________________________________________
Open-graphics mailing list
[email protected]
http://lists.duskglow.com/mailman/listinfo/open-graphics
List service provided by Duskglow Consulting, LLC (www.duskglow.com)
