Timothy Normand Miller wrote:
As I'm sure most of you are aware, we're testing OGD1 by putting a
semi-complete design into it with PCI, video, memory controller, etc.
We've run into a challenge with video, and we could use some
brain-storming help to solve it.
The problem has to do with async fifos. Check out the existing designs:
https://svn.suug.ch/repos/opengraphics/main/trunk/rtl/fifos/
The fifos of interest are the "async" fifos, which have head and tail
ends at different clock rates, and fifo_DxW.v, which uses one clock
domain and can be mapped to one or more of the large block RAMs on the
chip.
There might be some pipelining possible since you always know the next
value for both counters -- it is 1 more than the current count mod 512.
So, you have four possible outputs of comparing tail and tail + 1 with
head and head + 1. You can do the compares a clock ahead and then
decide which result to use based not on the output of the counters but
rather using the count input to the counters.
--
JRT
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