Timothy Normand Miller wrote:
On 2/13/07, James Richard Tyrer <[EMAIL PROTECTED]> wrote:
Timothy Normand Miller wrote:
> On 2/13/07, James Richard Tyrer <[EMAIL PROTECTED]> wrote:
You can't use the same memory for the dirty bits. They are going to
have to be separate from the data ram. This doesn't need to be actual 3
port ram since you have one port that is read only and two ports that
are write only and the write ports have arbitration depending on whether
the bit is 1 or 0 -- only one write port can be active at a time and
this is automatically arbitrated by the FIFO logic. You could use
synchronous SR flipflops for this if 512 flipflops isn't too much real
estate.
Understood. We'd just like to avoid wasting a block RAM for a
one-bit-wide fifo.
You don't think that you could do it in logic? rather than RAM.
A clocked SR is 4 gates. You need 2 gates for output (one for head and
one for tail) and you need 2 address decoders, and you need some logic
on the input side of the ffs.
On a FPGA I suppose that this would be 512 ff based cells plus something
for the 2 decoders.
Is there some way to use the same decoders as the RAM block since they
are decoding the same addresses?
How much simpler it is to think in terms of discrete parts. :-)
--
JRT
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