On 3/27/07, Koen De Vleeschauwer <[EMAIL PROTECTED]> wrote:
Hi.
A few questions about the General Purpose I/O Connector, P50E:
- The connector is described as "100 Pin IDC Connector". Is a datasheet
available of the connector which will be used? I would like to avoid any ambiguity as to
pin numbering and mating connector.
What we have is an array of holes in the board, spaced appropriately
for a particular connector to be attached. We can attach that
connector, but the connector is somewhat expensive. We're pondering
the idea of offering boards without the connector. Instead, there are
push-pins available that will fit into the holes that may be
appropriate for many kinds of projects.
The connector we selected has two rows of 50 pins, and the spacing is
the same as a PATA IDE connector. I don't recall how many pins are
ground.
- I assume the idea is to have OGD1 and daughterboard next to each other, with a 100-way
flat cable running between them. What max. cable length would be
"safe"/adviseable ?
The idea is to have general user I/O for whatever a hobbyist wants.
The board is designed, however, so that a mating connector could be
mounted on another board and then you can add reinforcement bars to
hold them together stiffly.
- The following three signals: SC_CLK, SCL_VSYNC, SC_BLANK* are on the
connector but do not ring a bell here. What does SC_ stand for?
One possible use for this is a video in device. Those would be sync
signals. If SC stands for something, I was never told it.
- Is putting two OGD1's in the same PCI bus, connecting a flat cable between
the IDC connectors, and running SLI/Crossfire over the flat cable a supported
hardware configuration? Merely joking, of course :)
It is if you have designed logic to take advantage of it. :)
--
Timothy Normand Miller
http://www.cse.ohio-state.edu/~millerti
Open Graphics Project
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