On Tue, Mar 27, 2007 at 11:55:41AM -0400, Timothy Normand Miller wrote: > Possibly. But keep in mind that adding options adds more cost than > the options themselves. That is, if X is the price of the board where > they all have the connector and Y is the cost of the board with the > connector where the base model lacks the connector, then Y will be > greater than X by an amount of money that you may not appreciate. >
OK. Understood. > We certainly have some clean-up to do on our documentation. However, > all of this will be provided in detail. For instance, part of the > OGD1 product is the "pad ring" which is the top-level Verilog module > that represents all of the pins on the FPGA. That module will contain > instantiation of I/O buffers, clock managers, etc. The next level > down will be basically the same set of pins, but grouped into busses > with descriptive names. From that alone, the pin assignments will be > obvious, but we will provide human-language documentation as well. Correct. You need to provide this documentation, both human readable and UCF. For the General Purpose I/O Connector, I already know which FPGA pins correspond to which IDC connector pins. All it takes is the schematics and a felt tip marker. I just don't know which pin on the board is pin A1, which pin is pin B50. regards, koen _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
