I miss this one :)
Globaly asynchronous/localy synchronous are a design technic where
each module use a standard synchonous logic, but connection between
each block are asynchrone. This permit different clock speed and avoid
all the nighmarre of having a clock at 1ns periode with 20ns of delay
depending where you read the clock inside the clock tree. The bigger
the design the worst the problem is.
Most (all?) SoC design are done like this.
So i didn't speak about asynchronous logic at all.
2007/3/24, Attila Kinali <[EMAIL PROTECTED]>:
On Sun, 18 Mar 2007 21:04:49 +0100
"Nicolas Boulay" <[EMAIL PROTECTED]> wrote:
> I just speak about the fact that 4 Ghz logic is not impossible.
> Because 6 Ghz (or 130 ps of propagation time) still exist. Usualy the
> problem are in the clock propagation time, but globaly asynchronous
> design could work at that speed.
Yes. But the industry still refrains from using any asynchron
design. Even GALS are only used in research, though they should
be quite straight forward to use.
(Ok, multiple cores are some very coars grained form of GALS,
but well...)
Attila Kinali
--
Linux ist... wenn man einfache Dinge auch mit einer kryptischen
post-fix Sprache loesen kann
-- Daniel Hottinger
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