Daniel Rozsnyó wrote:
If the UMA stuff from Rogelio will be possible (e.g. by designing a
new northbridge) wouldn't it be possible to make a
mass-multiprocessing mainboard using non-smp enabled cpus?
If the processor chip (actually package) has cache then you need to have
address "snoop" for cache coherency. This is an absolute requirement
for SMP.
You can, however, build a system that has asymmetrical multi-processors.
For example, you can have:
OS
User programs
X11 server
I/O including service of interrupts.
each handled by a separate processor. And the second two don't need to
be as powerful as the first two. In the case of the I/O processor, you
can have more than one as long as they are assigned different jobs --
this is how a mainframe does I/O (IBM calls these channels). Because
only *NIX will work this way (Windows won't) a system with these
features is rarely offered.
--
JRT
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