> > If the UMA stuff from Rogelio will be possible (e.g. by designing a > > new northbridge) wouldn't it be possible to make a > > mass-multiprocessing mainboard using non-smp enabled cpus? > > If the processor chip (actually package) has cache then you need to have > address "snoop" for cache coherency. This is an absolute requirement > for SMP. > > You can, however, build a system that has asymmetrical multi-processors. > > For example, you can have: > > OS > User programs > X11 server > I/O including service of interrupts. > > each handled by a separate processor. And the second two don't need to > be as powerful as the first two. In the case of the I/O processor, you > can have more than one as long as they are assigned different jobs -- > this is how a mainframe does I/O (IBM calls these channels). Because > only *NIX will work this way (Windows won't) a system with these > features is rarely offered.
Asymmetrical multi-processors were done before SMP. See the Goble VAX. Sort of a first step towards SMP. Then companies like Sequent and Pyramid came along and got SMP working. SMP has the advantage that you can dynamically allocate CPUs between OS and User as needed without creating a bottleneck. Today, the clock speed has risen to the point that you can't have one big (about 18 inches?) bus anymore. Thus NUMA. :-( The X11 server goes in the X terminal on the Ethernet. I/O processors don't have the same bottleneck issues, since you can predict the amount of CPU needed ahead of time. _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
