Terry Hancock wrote:
Hi all,
I'm creating some SVG graphics to explain some of what I have learned is
the process in taking logic design from concept to real hardware, and
I'd just like to see if I can get feedback on how well I've understood:
I found the intro from the Icarus Verilog wiki to be very useful:
http://iverilog.wikia.com/wiki/Introduction
as well as this page on programming Xilinx FPGAs:
http://www.polybus.com/xilinx_on_linux.html
Moving from concept to hardware:
0) As I understand it, we have a concept for an "Open Graphics
Architecture" (OGA) (completed)
1) We then have a C++ object model which expresses OGA (completed)
2) We then create a Verilog version of OGA (work in progress)
3) We can simulate and/or "synthesize" that Verilog OGA by using a
program like Icarus Verilog, and monitor its behavior with a "waveform
viewer" like GTKWave (possible now, for parts of OGA?).
The result of synthesis, called a "netlist" is the input for tools used
to program an FPGA or to design an ASIC.
4) A suite of tools from Xilinx are used to program the FPGA based on
the netlist. These seem to have a number of fairly unrelated names and
are all proprietary, although there is a freeware version of the
commandline tools that will run under WINE?
[jg]Probably better to get ISE webpack: "ISE WebPACK is the industry´s only FREE, fully featured front-to-back FPGA design
solution for Linux, Windows XP, and Windows Vista") skip a windows 98-b install...
5) The same netlist is also the input for creating an ASIC, but in that
case, the tools used will be more sophisticated, proprietary, and
possibly even custom in-house tools used by the ASIC manufacturer.
[jg]No, the tools will be used by you or a hired engineer, not the mfr...
You could make a low volume run via MOSIS, from layout done with FOSS Magic
layout editor,
and gemini layout vs schematic checker...The Gemini program is available via anonymous ftp. For details, contact
[EMAIL PROTECTED] used to compare the specified netlist
to the result of layout (including shorted well ties and other mistakes...)
(see http://www.cs.utexas.edu/users/skeckler/cs384v/cad/magic/docs/tut7.ps )
and also RSIM is a switch level simulator that tells you the results of FPGA
routing, or
hand and autorouting of an ASIC is generating good functions.
Here is some activity using these tools:
http://www.stanford.edu/class/ee272/doc/faq/magic.html
ftp://ftp.isi.edu/pub/sondeen/magic
So you could make a MOSIS chip yourself if you have the ante up money.
John Griessen
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