Moin
On Tue, 27 Nov 2007 17:28:52 -0500
"Timothy Normand Miller" <[EMAIL PROTECTED]> wrote:
> Then
> you can back-annotate the logical netlist with timing information that
> you get from P&R. If you simulate the original Verilog code, that's
> called an RTL-level simulation. If you simulate the back-annotated
> netlist, that's called a gate-level simulation.
I beg to differ. Simulating a back-annotated netlist is one
way of doing timing verification, but it is not a gate level
simulation. Gate level simulation means that you synthesized
your design in to a gate level description and simulate this
description to verify that the synthesizer did the conversion
correctly.
Attila Kinali
--
Praised are the Fountains of Shelieth, the silver harp of the waters,
But blest in my name forever this stream that stanched my thirst!
-- Deed of Morred
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