Timothy Normand Miller wrote:
On 11/28/07, Viktor Pracht <[EMAIL PROTECTED]> wrote:
What can the really expensive tools do that Icarus can't?
The really expensive tools are smart. Icarus, Synplicity, ISE's
"Smarter" would be a better word. "Smart" implies other tools are
"dumb", which is misleading. Also, I think it's important to separate
Icarus, which is designed for *simulation* (I don't know what the
synthesis quality is like), from Synplify/XST/Quartus, which all have
synthesis as their *only* goal.
synthesizer, and other basic ones like that aren't; they just make the
most direct translation from Verilog to technology cells. Then it's
Not so -- XST is timing-driven, as is Synplicity (and, I'm sure,
Quartus). Moreover, all of these tools do a substantial amount of
optimization on the network before handing it off to mapping, which is
likewise timing-driven, and is liable to do /further/ optimization
before handing it off to P&R. It's hardly "the most direct translation"
-- not by a long shot.
up to P&R to make it fit. The smart tools look ahead, consider timing
If it doesn't fit after mapping, there's nothing PAR can do about it.
Post-PAR resynthesis may be able to fix up timing, but that's about it.
Even that's pretty limited (decreasing levels usually means increasing
area, which is obviously problematic post-PAR as you can't afford to
tear up your placement and the routing penalty of just throwing your
resynthesized logic wherever there's room could be astronomical).
earlier in the process, and they'll refactor your logic to meet
constraints. You know how, hypothetically, any chunk of combinatorial
logic can be converted into two levels of AND and OR gates (with some
inverters). So if your logic doesn't meet timing, a smart tool can
Not just hypothetically -- you're referring to the sum-of-product (SoP)
or product-of-sum (PoS) form, and it's liable to be exponential to the
number of inputs (i.e., totally irrelevant for many practical circuits).
Not to mention the fact that you can't collapse an arbitrary network
to two levels when no node can have a fan-in greater than four (or six,
or however large your LUT is). I suppose these are among the "practical
limits" to which you refer, but I would argue that all the vendors'
synthesis tools push those same limits. Some admittedly do it better
than others, but none fail to do so entirely (except maybe Icarus, but
as I've said, it really isn't a synthesis tool in the same way XST is so
it's not really a fair comparison).
see that your logic has too many layers and reorganize it so that it
has fewer (up to practical limits). These toy FPGA tools don't do any
of that, or if they do anything like that at all, they do a lousy job
of it.
It's all well and good to opine that they're doing a lousy job; can you
substantiate that? I ask in a good-natured, inquisitive way; it seems
important, since on this list you're looked upon as an authority on such
things and, if that's just an unsubstantiated opinion or an
exaggeration, it might lead to a handful of budding hardware developers
to harbour unwarranted misgivings.
My opinion and experience on the subject is, I think, pretty well
articulated by this quote from an FPGA Journal article: "Be aware that a
synthesis tool winning on quality of results is like a politician
winning an election. Victory doesn't mean that every design or every
voter goes to the winner. In a reasonable benchmarking situation, the
winning tool might win 30% of designs, the losing tool might win 20%,
and the other 50% would be a tie." I think that's a much more realistic
assessment of how expensive tools compare with FPGA vendors' free
offerings (and probably Icarus, though again, its QoR is a mystery to
me). Saying one is "smart" and the other is "lousy" implies something
quite different.
In short, I don't think you're giving XST's QoR the credit it's due
relative to the Magma/Mentor/Synopsys offerings (usually, Synplify is
lumped in with those three, but you've inexplicably written it off).
Full disclosure: I worked on Xilinx's XST & MAP during an internship.
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