The difference between FPGA and ASIC is different standard cells
or no standard cells, and FPGA primitives, which are the building blocks you
choose from.
Standard cells are kind of similar, but the routing is completely free form
and up to you in ASICs, so you have to extract capacitance and resistance from
your layout results and model the interconnect to see if it still flies.
This is a low cost kind of ASIC that often still needs some interface circuitry
in discretes to do level translation, and protect the ASIC from static,
drive high power lines, etc.
With no standard cells, you are using the teeniest primitives,
transistors made from the design rules and wires and vias. You need
some deep understanding to work that way, but it can be needed for
making maximum current drivers, extra static discharge protection beyond
standard cells, etc.
John G
Timothy Normand Miller wrote:
On 11/27/07, Terry Hancock <[EMAIL PROTECTED]> wrote:
5) The same netlist is also the input for creating an ASIC, but in that
case, the tools used will be more sophisticated, proprietary, and
possibly even custom in-house tools used by the ASIC manufacturer.
No. We would synthesize the original Verilog code to target the ASIC,
which would be quite different from the FPGA, so the mapping to logic
blocks would be different.
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