On 11/27/07, Terry Hancock <[EMAIL PROTECTED]> wrote: > 2) We then create a Verilog version of OGA (work in progress) > > 3) We can simulate and/or "synthesize" that Verilog OGA by using a > program like Icarus Verilog, and monitor its behavior with a "waveform > viewer" like GTKWave (possible now, for parts of OGA?).
Narrowly, OGA is just a drawing engine, for which we have only some snippets of proofs-of-concept code for litle things like reciprocals, fp adders, etc. Broadly, OGA includes PCI, video, memory, etc., of which we have a number of important things completed. > The result of synthesis, called a "netlist" is the input for tools used > to program an FPGA or to design an ASIC. There are netlists at different levels of abstraction. There are technical names that I can't recall, but anyhow... You can have a logical netlist that is just the Verilog code converted into appropriate logic blocks for the target technology. Then you can, let me make up a word, physicalize it via place and route, which assigns physical locations and interconnects to those logic blocks. I guess you can call this a physical netlist, and unlikely to be in the same format as the logical netlist. EDID is used somewhere in there. Then you can back-annotate the logical netlist with timing information that you get from P&R. If you simulate the original Verilog code, that's called an RTL-level simulation. If you simulate the back-annotated netlist, that's called a gate-level simulation. > 4) A suite of tools from Xilinx are used to program the FPGA based on > the netlist. These seem to have a number of fairly unrelated names and > are all proprietary, although there is a freeware version of the > commandline tools that will run under WINE? Yes. Perhaps someone should figure out how to get the low-level tools (they're just win32 command-line tools) to run under WINE and then build a clone of the Xilinx Project Manager to wrap them. This would solve some of our problems. And so if you have a commercial license for the Xilinx tools, then you can get them to run under Linux. (lmgrd will have to be emulated, and we shouldn't cheat by faking it.) > 5) The same netlist is also the input for creating an ASIC, but in that > case, the tools used will be more sophisticated, proprietary, and > possibly even custom in-house tools used by the ASIC manufacturer. No. We would synthesize the original Verilog code to target the ASIC, which would be quite different from the FPGA, so the mapping to logic blocks would be different. -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
