Hi all, I'm creating some SVG graphics to explain some of what I have learned is the process in taking logic design from concept to real hardware, and I'd just like to see if I can get feedback on how well I've understood:
I found the intro from the Icarus Verilog wiki to be very useful: http://iverilog.wikia.com/wiki/Introduction as well as this page on programming Xilinx FPGAs: http://www.polybus.com/xilinx_on_linux.html Moving from concept to hardware: 0) As I understand it, we have a concept for an "Open Graphics Architecture" (OGA) (completed) 1) We then have a C++ object model which expresses OGA (completed) 2) We then create a Verilog version of OGA (work in progress) 3) We can simulate and/or "synthesize" that Verilog OGA by using a program like Icarus Verilog, and monitor its behavior with a "waveform viewer" like GTKWave (possible now, for parts of OGA?). The result of synthesis, called a "netlist" is the input for tools used to program an FPGA or to design an ASIC. 4) A suite of tools from Xilinx are used to program the FPGA based on the netlist. These seem to have a number of fairly unrelated names and are all proprietary, although there is a freeware version of the commandline tools that will run under WINE? 5) The same netlist is also the input for creating an ASIC, but in that case, the tools used will be more sophisticated, proprietary, and possibly even custom in-house tools used by the ASIC manufacturer. Is that all pretty much correct? Cheers, Terry -- Terry Hancock ([EMAIL PROTECTED]) Anansi Spaceworks http://www.AnansiSpaceworks.com _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
