Timothy Normand Miller wrote:
Sorry about the cross-post. We're -><- THIS close to getting OGD1
done, with artwork in the hands of board makers who are working on
quotes, and we've discovered a problem that could make the video
output unacceptable.
Also, please consider if the jitter can be reduced.
Is this measured jitter or the devices spec?
I presume that these jittery clocks are being generated by a PLL
frequency synthesizer in the FPGA.
http://www.edn.com/archives/1995/112395/24df5.htm
This specifically mentions power supply noise and ground bounce.
Basically, this comes down to reducing the noise on the PLL VCO input
power by adding a regulator or improving the bypass capacitor (which can
mean adding parallel small capacitors) and a larger ground buss and
proper routing of the output clock ground to the PLL input ground. It
is very difficult to bypass the ground because the bypass would need to
have much less series inductance than the ground lead -- easier to make
a larger ground lead -- although you can do this if we have a negative
supply.
Less likely, but easy to fix, would be that the rise time of the input
clock was too long, or that the drive current was insufficient, or the
input drivers.
Or, (very hard to fix) is that the system is suffering from ground bounce.
I am still having trouble with the schematic because I can't display the
whole thing on my small screen. So, could someone please help me with this.
Which IC is the relevant clock for the generation of the pixel clock (Y2
or Y3 perhaps). Where does the power to operate it come from? Which
power bypass capacitors are immediately next to the oscillator?
--
JRT
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