On Dec 2, 2007 4:30 AM, James Richard Tyrer <[EMAIL PROTECTED]> wrote: > Timothy Normand Miller wrote: > > On 11/30/07, Vesa Solonen <[EMAIL PROTECTED]> wrote: > >> > >> On Fri, 30 Nov 2007, Timothy Normand Miller wrote: > >> > >>> to the clock you're generating. The digital problem we're seeing is > >>> high-frequency jitter, while the analog one is much lower frequency, > >>> on the order of a few Hz. Indeed, I suspect that a PLL with > >> Umm I see, are you certain that there is no ground-loop problem in your > >> test setup? That analog jitter of few Hz may be some beat with mains > >> frequency and vsync. Or ground loop on the pcb... > > > > This could be a factor. What I do know, however, is that switching to > > alternate clock generators clears up the problem significantly. > > > That is alternate clock generators on the FPGA chip?
Either external ones or ones in the Lattice XP10, which appear to be MUCH better than the Xilinx ones. -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
