Timothy Normand Miller wrote:
On 11/29/07, James Richard Tyrer <[EMAIL PROTECTED]> wrote:
Timothy Normand Miller wrote:
Sorry about the cross-post. We're -><- THIS close to getting OGD1
done, with artwork in the hands of board makers who are working on
quotes, and we've discovered a problem that could make the video
output unacceptable.
Also, please consider if the jitter can be reduced.
Is this measured jitter or the devices spec?
Measured. The jitter we're observing is much worse than the spec.
That seems to be a common problem, and we're also dealing with types
of jitter that specs don't even mention. For instance, low-frequency
jitter tends not to be a problem when you're all digital, but it's
something you can see on an analog monitor.
I presume that these jittery clocks are being generated by a PLL
frequency synthesizer in the FPGA.
They're DCMs, not PLLs. They're "all digital."
Something to be said for older chips that had PLLs and separate power
supplies for them. These appear to be based on delay lines rather than
digital PLLs. It looks like the method is always going to cause clock
jitter.
I didn't find Xilinx's app note very helpful:
http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf
I don't really think that using the ground guard pins is going to solve
the problem.
Perhaps an external clock generator is going to be needed.
--
JRT
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