On 11/30/07, Vesa Solonen <[EMAIL PROTECTED]> wrote: > On Thu, 29 Nov 2007, Timothy Normand Miller wrote: > > > The crystal has negligable jitter. It's the DCM in the Xilinx chip > > that's introducing all of the noise. A lot of it comes from ground > > bounce and crosstalk from other activity in the FPGA. We actually > > You probably have read the following > http://www.xilinx.com/support/documentation/application_notes/xapp462.pdf
Ages ago, yes. Howard's probably read it more recently. One thing that people aren't necessarily aware of is that PLLs tend to report only theoretical jitter. VCOs are vulnerable to power supply fluctuations and ground bounce too, so that's a major factor. There are also different kinds of jitter at different frequencies relative to the clock you're generating. The digital problem we're seeing is high-frequency jitter, while the analog one is much lower frequency, on the order of a few Hz. Indeed, I suspect that a PLL with relatively high theoretical jitter could be better for video applications than some other PLL with better theoretical characteristics. Oh, and this stuff is at the far edges of my knowledge. Howard tells me stuff, I mostly understand, and I post questions. Unfortunately, I don't understand it much beyond what he told me. I mean, I get the basic principles behind PLLs and DCMs, but nothing too specific. -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
