2007/12/15, James Richard Tyrer <[EMAIL PROTECTED]>: > Nicolas Boulay wrote: > > 2007/12/15, James Richard Tyrer <[EMAIL PROTECTED]>: > >> And more hardware is more hardware so it will obviously run the > >> problem faster. > > > > That the point ! > > Yes, and where do we get this additional hardware (that is more hardware > than 16 32bit float MACs would require)? > > > You completly over-estimate the size of the control logique compare > > to the size of a fast FPU. That's at least one order of magnitude > > smaller. > > Microcode has very little control logic because the microcode tells > everything what to do. OTOH, a systolic array has no control logic. >
Compare to fpu, control logic look like peanuts... And for simple, risc like cpu, microcode have no use... > > To take the issue from an other point of view : a 3 scalar core GPU > > will be faster and smaller than a 4 way SIMD core GPU. > > Yes, 3 is less than 4. In fact, it is exactly 1 less. So why not > compare equivalents? Are you saying that a 3 scaler core GPU will be > faster and smaller than a 3 way SIMD core GPU? > I though exactly what i write to make it more evident. A fat big _4_ SIMD single core will be most of the time slower than a GPU with _3_ scalar core. And yes, it's evident that 3 fpu will use a smaller die than 4. > If so, then start by clearly defining: > > 3 scalar core GPU > 3 way SIMD core GPU > > > I speak about shader code, not about the generic 3D pipeline. > > Shader code _is_ matrix and vector code. We are operating on pixels. > Color pixels *are* vectors! Reread my first post. Most of (complexe) shader code are _not_ vector code. I don't speak on generic terme, i speak about real world example of current complexe vector shader and pixel shader. > > -- > JRT > _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
