Nicolas Boulay wrote:
2007/12/14, James Richard Tyrer <[EMAIL PROTECTED]>:
Patrick McNamara wrote:
http://www.opensparc.net/news/2007-12/tgdaily-sun-open-sources-t2-processor.html
This (unlike the T1) supports all VIS instructions (except Quad
precision) and the FGX processor (SIMD).
It is actually the FGX processor which would be of interest to us.
I have wondered if it would be possible to have a graphics
processor based on multiple SIMD processors from standard MPUs. I
was thinking of the AltiVec; however, the SPARC is available free.
SIMD have no use for shader program. multiple scalar core are much
more efficient. The issue is then the connection network.
I have to wonder if you actually know what the hardware for a shader is.
And if you know what the AltiVec hardware is. Or, perhaps you know
what the MMX/3DNOW/SSE/SSE2/SSE3 hardware is.
What we have is 4 32bit registers on which we can execute a single
instruction which will operate on the 4 registers at once. The
instructions ARE the instructions which are needed to implement 3D
hardware graphics (wonder why AMD called it 3DNOW). In short, the SIMD
graphics hardware in the Pentium/Athlon, PowerPC, UltraSPARC is a
shader. A shader operates on vector and matrix data types (read OpenGL
Shader Language) which means that it MUST BE SIMD (VectorProcessor ==
SIMD -- I prefer VectorProcessor since all instructions don't do exactly
the same thing to all of the data).
The current ATI and nVidia chips are extensions of SIMD. They are still
SIMD. The difference is that the processing units do not have fixed
assignments.
The above considered, just exactly what do you mean?
That said, why would we want to use an existing hardware design. Simple
reason, we would already know that it works and could save several years
of R&D.
The problem with multiple independent processors is that each processor
must be fed data and instructions. This requires a buss system. There
are limits to the practical width of a parallel buss system. So, large
systems must go to a crossbar system. Considering the massive crossbar
which would be needed for all of the processing units to be totally
separate scalar units, I would guess that ATI & nVidia have some
semi-fixed organization for the assignment of processing units to data
and instructions.
The real point is that with a 4 word vector processor that the amount of
computing by the "t" processor is much less than the "x" processor. I
have already mentioned the possibility of having, for example, 4 4-word
vector processors (SIMD) but only using 8 processing units to implement
them based on the same theory that all of the operations won't always
need 4 processors (and would simply have to wait if enough processors
weren't available).
--
JRT
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