I had a look at the IO unit in HQ and your wrapper. If you're already
on track to integrate the HQ, you may ignore this, but my idea and
questions of how to this is,
* Do we keep the val_or_addr[0] indicator for inport vs outport? I
see no reason not to, we'll just revise hqio.asm at the end.
* We route out the port address and data i/o from HQ, something like
module oga1hq(
...
output [8:0] io_addr,
output io_enable, // read or write depending on io_addr[0]
output [31:0] io_write_data,
input [31:0] io_read_data);
* We instantiate oga1hq inside hq_wrapper.
* We implement a port address decoder inside hq_wrapper.
One thing which is not clear to me is what to register at what needs to
be combinatorial. I think the critical part is reads. The input ports
needs to be decoded from the port address (val_or_addr) and fed back to
HQ and multiplexed into wb_val_o in one cycle, or is there another way?
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