On Fri, Aug 1, 2008 at 2:59 AM, Petter Urkedal <[EMAIL PROTECTED]> wrote: > On 2008-07-31, Timothy Normand Miller wrote: >> ## PCI_TW_COUNT would be wired to pci2hq_cmd_count > > Thus, I renamed PCI_TW_COUNT to PCI_T_CMD_COUNT. > >> // Assign dequeue signals if port read. >> if (hqio_enable_in) >> case (hqio_addr) >> MEM_READQ_DATA: >> hq2br_deq_read <= 1; >> PCI_TW_DATA, PCI_TR_ADDR: >> >> ## Looks like these are really the same register. They both get data >> from exactly the same place and dequeue in the same way. Perhaps it >> should be called PCI_CMD_DATA or something that fits with the scheme. >> Write address, read address, write data, and read count all come from >> the same bits of the same queue. > > It's now PCI_T_CMD_DATA. > >> ## Ok, looks good. Now, we need the bypass mode. > > Thanks for all the hints. I just committed what I had time for before > going to work. What remains is the bypass mode and the 3 upper bits of > PCI_T_CMD_INFO (target).
After the discussion with Mark and thinking about it a bit, I'm going to switch on the decode logic for BAR2, but at a fixed address and size, and there will be an enable bit in config space to turn it and VGA I/O on. To HQ, it will appear as BAR2. -- Timothy Normand Miller http://www.cse.ohio-state.edu/~millerti Open Graphics Project _______________________________________________ Open-graphics mailing list [email protected] http://lists.duskglow.com/mailman/listinfo/open-graphics List service provided by Duskglow Consulting, LLC (www.duskglow.com)
