On Thursday 15 December 2011 22:15:20 Matthew Hicks wrote: > The current or1200 implementation allows any value to be written to r0, > which is supposed to always be 0. The following patch basically ignores > all writes to r0. > > Index: or1200_rf.v > =================================================================== > --- or1200_rf.v (revision 672) > +++ or1200_rf.v (working copy) > @@ -186,7 +186,7 @@ > // > // RF write data is either from SPRS or normal from CPU datapath > // > -assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw; > + assign rf_dataw = (rf_addrw == 0) ? 32'b0 : (spr_valid & spr_write) ? > spr_dat_i : dataw; > > // > // RF write enable is either from SPRS or normal from CPU control
Leaving discussion of whether this is a good thing to do aside, I think your patch has a problem. The register file is normally a block memory, and does not get reset (for instance, the Actel FPGAs cannot). So you should probably place your r0=0 code on the read side, at which point the write limiting logic becomes a bit pointless (power savings from not writing r0 - which only happens during init, now - probably far outweighed by testing for rW=r0 on all cycles). _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
