On Fri, Dec 16, 2011 at 6:29 AM, Yann Vernier <[email protected]> wrote:
> > Leaving discussion of whether this is a good thing to do aside, I think > your > patch has a problem. The register file is normally a block memory, and > does not > get reset (for instance, the Actel FPGAs cannot). So you should probably > place > your r0=0 code on the read side, at which point the write limiting logic > becomes a bit pointless (power savings from not writing r0 - which only > happens during init, now - probably far outweighed by testing for rW=r0 on > all > cycles). > I know that for Xilinx the register file is implemented using two block RAMs which have their contents initialized to zero on start-up. If this is true of other FPGAs, then there should be no problem. In cases where the reg file is uninitialized RAM, software generally initializes it anyway, which will cause a write of 0 to r0. By the way r0 is still written using my patch, it just always is written with a value of zero. As far as using r0 as an special backup register for exception handlers, this would create unportable code given the lack of direction from the architecture specification and assumes that the interrupted code isn't r0 for its own special purposes. To me, there is no way software can safely treat r0 as anything but 0. Without a clear definition of the behavior of r0, it is turtles all the way down. ---Matthew Hicks
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