Hi all:
The or1ksim simulator should not initialise the CPU general purpose
registers with zero values, because that's not what happens on the real
or1200 core, and even if it did, there is no such guarantee in the
OpenRISC architecture specification.
I would set them all to random values when simulating a CPU reset
(especially R0), thus encouraging everybody to initialise all necessary
registers properly on start-up.
Because of the or1ksim's current "convenient" behaviour, I have to patch
most of its test suite so that it works when running under ORPSoCV2's
Verilog simulation. Provided that my previous patches get applied, I'll
be posting new patches for or1ksim's test suite in the next days.
Regards,
R. Diez
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