That's a sensible approach. Do you mean just the GPRs or all the SPRs as
well?
> [...]
> If you post the patch, I'll review and am happy to apply it for you.
I'm not familiar with the other SPRs yet. Please find attached a patch
for the GPRs.
Thanks,
Ruben
Index: cpu/or32/execute.c
===================================================================
--- cpu/or32/execute.c (revision 787)
+++ cpu/or32/execute.c (working copy)
@@ -848,9 +848,24 @@
runtime.cpu.supercycles = 0;
runtime.cpu.hazardwait = 0;
+ // In the architecture specification there is no guarantee that R0 is
hardwired to zero.
+ // In fact, there is no guarantee that any of the General Purpose Registers
will be
+ // zeroed on start-up, and indeed the or1200 Verilog core usually does not
clear them.
+ //
+ // However, the or1ksim simulator did clear all GPRs in the past, which lead
to suprises
+ // later on when running the software on real hardware.
+ //
+ // In the future, or1ksim will have a new configuration setting that will
provide
+ // a more flexible way to initialise the GPRs on reset. Until then, all
registers
+ // are now initialised to a known, non-zero value, see below. This should
encourage
+ // the software developers to initialise all necessary GPRs on start-up, and
thus
+ // reduce the chances for suprises down the line.
+ const uorreg_t gpr_reset_value = 0x12345678;
+
for (i = 0; i < MAX_GPRS; i++)
{
- setsim_reg (i, 0);
+ // Note that we cannot use setsim_reg() here, as that routine has an
exception for R0.
+ cpu_state.reg[i] = gpr_reset_value;
}
memset (&cpu_state.iqueue, 0, sizeof (cpu_state.iqueue));
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