On Tue, 2012-03-20 at 20:48 +0100, R. Diez wrote: > Hi all: > > The or1ksim simulator should not initialise the CPU general purpose > registers with zero values, because that's not what happens on the real > or1200 core, and even if it did, there is no such guarantee in the > OpenRISC architecture specification. > > I would set them all to random values when simulating a CPU reset > (especially R0), thus encouraging everybody to initialise all necessary > registers properly on start-up.
It would be best for Or1ksim to provide this as a configuration option, just as it does for memory initialization. Or1ksim is intended to model multiple architectural variants and implementations, so this gives the user greatest flexibility. > Because of the or1ksim's current "convenient" behaviour, I have to patch > most of its test suite so that it works when running under ORPSoCV2's > Verilog simulation. Provided that my previous patches get applied, I'll > be posting new patches for or1ksim's test suite in the next days. I'm slightly concerned you have to patch most of the Or1ksim test suite. I would have thought that was just a one line patch to explicitly zero R0 in the handful of bootloaders (I know there is more than one) used for low level programs. I thought newlib already had this fix in, so it should not affect any higher level programs. Jeremy -- Tel: +44 (1590) 610184 Cell: +44 (7970) 676050 SkypeID: jeremybennett Email: [email protected] Web: www.embecosm.com _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
