On Fri, Mar 23, 2012 at 5:07 PM, R. Diez <[email protected]> wrote: > >> That's a sensible approach. Do you mean just the GPRs or all the SPRs as >> well? > >> [...] > >> If you post the patch, I'll review and am happy to apply it for you. > > I'm not familiar with the other SPRs yet. Please find attached a patch for > the GPRs. >
This patch seems good to me and appears to achieve what you want. Regarding the SPRs, I believe most are defined at reset and or1ksim should be setting those appropriately. Whether they are or not is a different story, but in general I don't think preloading them with a known junk value is necessary. This is actually a good point to bring up - looking at the ISA it looks like things like TLB cache entries _should_ be reset. In particular the TLB match registers (the ones we look at to determine if the address we want is available in the cache) have their valid bit (bit 0) set to '0' on reset, while the VPN (bits 31-13) are 'X', clearly indicating that these should be reliably reporting TLB misses (due to invalid entries) after hardware reset. This has implications for the OR1200 I believe. Regarding or1ksim, though, In my opinion what would be the best solution to all of this is keeping track of the register accesses after "power up" on the simulator and printing out a big error message if accesses to any register which should be initialised (basically just the GPRs) are accessed without. This would mean wrapping them in some accessor function and checking against a "read_before_written" bit once after or1ksim bringup. Cheers Julius _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
