> remove the delay slot. It took me only about a week, and the > simulator passes all tests. I honestly don't think it would be too > much work to get the linux port working. > [...] > I really, really need an ISA without a delay slot for the work I'm > doing, so I'm going to continue working on it anyway. At the moment > [...]
That sounds very interesting indeed. Have you got a modified Verilog CPU core too? What are you plans with regards to the OpenRISC community? Are you working on a single project, or do you think you could contribute to OpenRISC for a longer period of time? Thanks, rdiez _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
