On Sun, Apr 22, 2012 at 10:28 PM, R. Diez <[email protected]> wrote: > That sounds very interesting indeed. Have you got a modified Verilog CPU core > too?
I'm working on a core in VHDL that I've started from scratch. I didn't start with the OR1200 because my group uses VHDL primarily and because the pipeline isn't structured in a way that was useful for us. (By structure, I mean the verilog source and the modules it's broken down into.) > > What are you plans with regards to the OpenRISC community? Are you working on > a single project, or do you think you could contribute to OpenRISC for a > longer period of time? > Well, I do intend on releasing the core I'm working on once it's in a somewhat usable state. I really like the OpenRISC ISA compared to other ISAs, *especially* since it's open and unencumbered by patents and so on, so yes, I'll continue contributing as much as time and my other obligations allow :) -Pete _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
