On Tue, Apr 24, 2012 at 9:47 PM, Peter Gavin <[email protected]> wrote: > On Tue, Apr 24, 2012 at 6:12 PM, Julius Baxter <[email protected]> wrote: >> Basically all new features will need to be indicated like this. As the >> reserved SPR space should read as zero, then existing implementations >> are safe, and new ones can just set the appropriate bits to '1'. It >> will be backwards sometimes, but oh well. Better than no indication at >> all. > > I'm thinking now this bit belongs in CPUCFGR, since that's where other > ISA and compatibility information is.
Hi Pete I was going to pull you up on this too. There's no way this bit should be in the SR! CPUCFGR sounds good, it shows the choice of optional architectural features supported by the implementation, and the no-delay-slot bit should fit in fine there. Can you go and complete the details of your proposal here: http://opencores.org/or1k/Architecture_Specification#Delay_Slot_Optional Cheers Julius _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
