On Tue, Apr 24, 2012 at 4:49 PM, Peter Gavin <[email protected]> wrote: > On 04/24/2012 05:06 PM, Ouabache Designworks wrote: >> >> >> >> Personally I would have gone with positive logic where you have a delay >> bit that is 1 when you have a delay and 0 when you don't. > > > The reason I chose the opposite was that for the current architecture with > the delay slot, the hard-wired value of 0 that is currently specified in the > manual would be unchanged. >
Basically all new features will need to be indicated like this. As the reserved SPR space should read as zero, then existing implementations are safe, and new ones can just set the appropriate bits to '1'. It will be backwards sometimes, but oh well. Better than no indication at all. Julius _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
