On Tue, Apr 24, 2012 at 6:12 PM, Julius Baxter <[email protected]> wrote: > Basically all new features will need to be indicated like this. As the > reserved SPR space should read as zero, then existing implementations > are safe, and new ones can just set the appropriate bits to '1'. It > will be backwards sometimes, but oh well. Better than no indication at > all.
I'm thinking now this bit belongs in CPUCFGR, since that's where other ISA and compatibility information is. Perhaps bit 10? -Pete _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
