On 04/24/2012 05:06 PM, Ouabache Designworks wrote:
Personally I would have gone with positive logic where you have a delay bit that is 1 when you have a delay and 0 when you don't.
The reason I chose the opposite was that for the current architecture with the delay slot, the hard-wired value of 0 that is currently specified in the manual would be unchanged.
-Pete _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
