From: "Julius Baxter" <[email protected]> Date: Sep 8, 2014 12:04 AM Subject: Re: mor1kx and counting clock cycles? To: "Ricardo Nobre" <[email protected]> Cc:
> > On Sep 7, 2014 11:53 PM, "Ricardo Nobre" <[email protected]> wrote: > > > > Hi Julius, > > > > I discovered the amazing OpenRISC, and more specifically mor1kx, when browsing the internet for open source cores. > > > > I managed to use 'fusesoc' to simulate, using verilator, a SoC with a mor1kx processor. > > > > I have a set of C DSP kernels that I compiled to the OR1000 ISA using the or1k-gnu toolchain. > > > > I run the compiled kernels on the simulated mor1kx using the folloing command (example for the dsp_mul32 kernel): > > fusesoc sim --sim verilator mor1kx-generic --elf-load /home/ricardo/mintsoc/tests/vltsim-test/dsp_mul32 > > > > Everithing works perfect, and I get the following message: > > Success! Got NOP_EXIT. Exiting (84104) > > Simulation ended at PC = 000031b4 (84105) > > > > At this point I'm so impressed that there is such a thing as a open source SoC that works, that I want to include metrics taken on the 'mor1kx' cores in a report that I'm doing as part of my PhD work. > > > > > > I just need to know how can I know the cycles taken by the 'mor1kx' core for executing each of my compiled kernels. > > Is there a OpenRISC intruction (that accesses some special register?) I can use to know how many clock cycles were used untill the end of the execution of each test kernel? > > Or is there any other way to get this information? (maybe verilator can report me cycle counts... I'm not an expert in verilator). > > Hi Ricardo, > > That's a very good question. Basically there isn't an official instruction, but I think it would be a very good exercise to add the instrumentation to take cycle counts. It could be done via the use of the l.nop (no op) instructions which allow an arbitrary immediate to be passed in their encoding which the simulated model and it's infrastructure can then so something based upon. > > I believe or1ksim might already have support for some cycle counter l.nop instructions, and the l.nop immediate is likely already defined (check an OR1k spr-defs.h file). So you could certainly add such a feature to the testbench in fusesoc to enable cycle counters. > > I'm CCing the OpenRISC lists as it might be the case that some verilog testbench infrastructure, like you want to add, might already exist. > > > > > Best regards and good luck with this very fine project! > > Thanks for the kind words! > > Cheers > > Julius
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