On Mon, Sep 15, 2014 at 5:16 AM, Sébastien Bourdeauducq <[email protected]> wrote: > On 09/15/2014 02:49 AM, BAndViG wrote: >> By the way, I run coremark today on atlys board SoC (latest mor1kx >> cappuccino pipeline) and measured 99.800399 Iterations/sec, that means >> 99.800399/ 50 MHz = 1,996. What is exactly value for LM32? > > I've done tests in May/June with LM32 and mor1kx at 83 1/3MHz, and I > measured 133 iterations/s in both cases, so the score I got was 1.6. > This is my mor1kx configuration: > https://github.com/m-labs/misoc/blob/master/misoclib/mor1kx/__init__.py > > This is slower than yours - are you using a faster configuration, or did > mor1kx improve in the meantime? >
Compiler flags might make a difference, IIRC I've got 142 iterations/sec with your setup/SoC and -O2 -mhard-mul -mhard-div. Also, from prior tests I have done, the memory foot-print of coremarks is somewhere between 4K and 8K, so you will notice increases in the coremark score by increasing the cache size up to 8K. So to get fair comparison results, you'd need to increase the cache size from 4K -> 8K, unfortunately it seems that LM32 can't meet the timing in your (ppro) SoC when doing that (mor1kx does). coremark numbers aside, there are a couple of features that mor1kx have that lm32 lack that could make an advantage performance-wise in other situations. 1) Support for wrapping burst cache refills. I.e. it will stall until the whole cache line is filled, but rather proceed when the requested address is fetched from memory. 2) Store buffer. Both LM32 and mor1kx has write-through caches, but mor1kx will not stall until the memory access has finished if the store buffer is enabled. 3) Multiway (>2) caches with LRU replacement strategy. Stefan _______________________________________________ OpenRISC mailing list [email protected] http://lists.openrisc.net/listinfo/openrisc
